1. Technical Field
The present disclosure relates to the technical field of electronic integrated circuits with adjustable capacitances. Particularly, the present disclosure relates to a regulation device of a variable capacitance in an integrated circuit having a time parameter depending on such capacitance.
2. Description of the Related Art
As it is known, in the field of the electronic circuits integrated on a chip of semiconductor material, a capacitance value of an integrated capacitor, such as the value of an integrated resistor, strongly depends on the manufacturing process. Particularly, in the integrated circuits having filters, the cut-off frequency of which is determined by a RC product, or ramp generators, in which the ramp slope itself depends on the C/I ratio, the spreads of the values of the resistor-capacitance product and the capacitance-current ratio, caused by the manufacturing process, compared to prefixed values, are significant and reach ±50%.
In order to limit such effects, for example, in the case of integrated filters, it is provided to implement a modular structure of capacitors in which the capacitance C is variable in order to regulate the RC product. Such modular structure, shown by way of example in FIG. 2 with the reference 200 in the case of a 4-bit regulation, includes a reference capacitor CF that can be connected in parallel to a plurality of capacitors C1, C2, C3, C4, or modular capacitive elements, which are binarily weighed (1C, 2C, 4C, 8C) starting from a minimum unit capacitance 1C. Particularly, each capacitor C1, C2, C3, C4 of the plurality is selectively connectable in parallel to the reference capacitor CF or disconnectable therefrom after the activation/deactivation of corresponding switches S1-S4 that are controlled by binary logic signals (0 and logic 1) B0, B1, B2, B3.
Generally, such control logic signals B0, B1, B2, and B3 are generated by a feedback regulation device associated with the integrated filter of the type known by a person skilled in the art. Particularly, such regulation device includes a block of capacitors that is substantially analogous (except for scale differences) to those of the modular structure 200 of FIG. 2.
As it is known, the above-mentioned fedback regulation device operates by trial and error, for example, by successive approximations, until determining an overall capacitance value of the capacitor block such as to make the filter RC product value proximate to that predetermined by the design specifications with residual error compatible to the preset accuracy percentage. In other words, if the RC product of the integrated filter is a maximum following the process spreads, to obtain the desired value a minimum capacitance C value is used, usually the reference capacitor CF value (the other capacitors will be excluded from parallelisms with the latter one). Vice versa, if the RC product is a minimum after the process, it is necessary to increase, by successive approximations, the reference capacitance CF value, by selectively placing it in parallel to the latter some or all the capacitors C1, C2, C3, C4.
At the end of the regulation step, the regulated capacitance C value is associated with a regulation sequence formed by the binary logic signals B0, B1, B2, and B3. Such regulation sequence, sent on a bus to the integrated filter, represents the sequence of control signals for the modular structure 200 capacitors C1, C2, C3, and C4.
Such known technique of regulating a capacitive value is not free from drawbacks.
In fact, during each step of the regulation operation, upon variation of the logic values assumed by the signals B0, B1, B2, B3, the number and the capacitance value of the capacitors C1, C2, C3, C4 that are selectively placed in parallel to the reference capacitor CF, change until reaching the capacitance value that is useful for the self-regulation. Therefore, the total capacitance of the capacitor block varies in percentage in a different manner according to the number of capacitors placed in parallel therebetween in a given instant. For example, if the capacitor C1 is added to the reference capacitor CF, the capacitance percentage variation determined by the addition of C1 will be C1/(CF+C1). If, on the contrary, the capacitor C1 is added when the other capacitors C2, C3, and C4 are already enabled, the percentage increase provided by C1 will be equal to C1/(CF+C1+C2+C3+C4).
Consequently, if the RC product is lower than a value that has been preset during the design step, following the manufacturing process, the capacitance percentage variation that is achieved with a minimum unit capacitance (i.e., varying a regulation bit), is different from the variation that could be obtained by adding such minimum capacitance for RC values higher than the preset value. Particularly, if the RC is lower than the preset value (therefore a number of capacitors have to be connected in parallel therebetween at the moment of the last bit assessment), then the percentage variation of the regulated capacitance achieved by adding a single unit capacitor is lower than the one that would be obtained if the RC would have been higher than the preset value.
It shall be noticed that the regulation devices of the known type are generally arranged to ensure the required accuracy (for example, 5%) in the worst case, i.e., in the case in which the RC product, at the end of the process, is higher than the value that has been predetermined in the design step. However, the Applicant noticed that, if, on the contrary, the RC product is lower than the preset value after the process, the accuracy ensured by such known regulation devices is much higher than that required (for example, 2%).
This demonstrates the inefficiency of the known regulation solution, since, in order to ensure the required accuracy, in the worst case the trend is to increase the regulation bits, i.e., to increase the number of the capacitances involved and, consequently, increase the cost in terms of area that is occupied by the integrated circuits.